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19-1156; Rev 2; 6/98
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8
__________________General Description
The MAX1242/MAX1243 are low-power, 10-bit analogto-digital converters (ADCs) available in 8-pin packages. They operate with a single +2.7V to +5.25V supply and feature a 7.5s successive-approximation ADC, a fast track/hold (1.5s), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 3mW (VDD = 3V) at the 73ksps maximum sampling speed. A 2A shutdown mode reduces power at slower throughput rates. The MAX1242 has an internal 2.5V reference, while the MAX1243 requires an external reference. The MAX1243 accepts signals from 0V to VREF, and the reference input range includes the positive supply rail. An external clock accesses data from the 3-wire interface, which connects directly to standard microcontroller I/O ports. The interface is compatible with SPITM, QSPITM, and MicrowireTM. Excellent AC characteristics and very low power combined with ease of use and small package size make these converters ideal for remote-sensor and dataacquisition applications, or for other circuits with demanding power consumption and space requirements. The MAX1242/MAX1243 are available in 8-pin DIP and SO packages.
________________________________Features
o +2.7V to +5.25V Single-Supply Operation o 10-Bit Resolution o Internal 2.5V Reference (MAX1242) o Small Footprint: 8-Pin DIP and SO Packages o Low Power: 3.7mW (73ksps, MAX1242) 3mW (73ksps, MAX1243) 66W (1ksps, MAX1243) 5W (power-down mode) o Internal Track/Hold o SPITM/QSPITM/MicrowireTM 3-Wire Serial Interface o Pin-Compatible 12-Bit Upgrades: MAX1240/MAX1241
MAX1242/MAX1243
_________________Ordering Information
PART MAX1242ACPA MAX1242BCPA MAX1242ACSA MAX1242BCSA MAX1242AEPA MAX1242BEPA TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PINPACKAGE 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 Plastic DIP 8 Plastic DIP INL (LSB) 1/2 1 1/2 1 1/2 1
Applications
Portable Data Logging Test Equipment Isolated Data Acquisition Process Control Monitoring Temperature Measurement
Ordering Information continued at end of data sheet. Note: Order the MAX1242A in place of the MAX1242C. Order the MAX1242B in place of the MAX1242D.
________________Functional Diagram Pin Configuration
CS 7 8 3 CONTROL LOGIC INT CLOCK VDD 1 SCLK SHDN
TOP VIEW
VDD AIN
1 2
8 7
SCLK CS
AIN 2 T/H 2.5V REFERENCE REF 4 MAX1242 ONLY 5 GND 10-BIT SAR
OUTPUT SHIFT REGISTER
6
DOUT
SHDN 3 REF 4
MAX1242 MAX1243
6 5
DOUT GND
MAX1242 MAX1243
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468.
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V AIN to GND................................................-0.3V to (VDD + 0.3V) REF to GND ...............................................-0.3V to (VDD + 0.3V) Digital Inputs to GND...............................................-0.3V to +6V DOUT to GND............................................-0.3V to (VDD + 0.3V) DOUT Current ..................................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 9.09mW/C above +70C) ...........727mW SO (derate 5.88mW/C above +70C)........................471mW CERDIP (derate 8.00mW/C above +70C)................640mW Operating Temperature Ranges MAX1242/MAX1243_C_A ..................................0C to +70C MAX1242/MAX1243_E_ A ..............................-40C to +85C MAX1242/MAX1243_MJA ............................-55C to +125C Storage Temperature Range............................-60C to +150C Lead Temperature (soldering, 10sec)............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V; 73ksps; fSCLK = 2.1MHz (50% duty cycle); MAX1242--4.7F capacitor at REF pin, MAX1243--external reference; VREF = 2.5V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) (Note1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps,SCLK =2.1MHz) 2.5p-p, 73ksps, f fSCLK = 2.1MHz) Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Input Capacitance 0 16 VREF V pF tAP tCONV tACQ fSCLK = 2.1MHz Figure 9 30 <50 5.5 7.5 1.5 73 s s ksps ns ps SINAD THD SFDR -3dB rolloff Up to the 5th harmonic 66 -70 70 2.25 1.0 dB dB dB MHz MHz DNL MAX124_A MAX124_B No missing codes over temperature MAX124_A MAX124_B MAX124_A MAX124_B 0.25 10 0.5 1.0 1 1 2 1 2 LSB ppm/C LSB Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; 73ksps; fSCLK = 2.1MHz (50% duty cycle); MAX1242--4.7F capacitor at REF pin, MAX1243--external reference; VREF = 2.5V applied to REF pin; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS TA = +25C (Note 4) MAX1242 0mA to 0.2mA output load 4.7 1.00 100 25 0.01 VDD + 50mV 150 10 MIN 2.470 TYP 2.500 30 0.35 MAX 2.530 30 UNITS V mA ppm/C mV F INTERNAL REFERENCE (MAX1242 only) REF Output Voltage REF Short-Circuit Current REF Temperature Coefficient Load Regulation (Note 5) Capacitive Bypass at REF EXTERNAL REFERENCE (VREF = 2.5V) Input Voltage Range Input Current Input Resistance REF Input Current in Shutdown Capacitive Bypass at REF DIGITAL INPUTS: SCLK, CS, SHDN SCLK, CS Input High Voltage SCLK, CS Input Low Voltage SCLK, CS Input Hysteresis SCLK, CS Input Leakage SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current SHDN Input Mid Voltage SHDN Voltage, Floating SHDN Max Allowed Leakage, Mid Input DIGITAL OUTPUT: DOUT Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Supply Voltage VDD Operating mode (MAX1242) Operating mode (MAX1242) Supply Current IDD VDD = 3.6V VDD = 5.25V VDD = 3.6V Operating mode (MAX1243) VDD = 5.25V VDD = 3.6V Power-down VDD = 5.25V VDD = VDD(min) to VDD(max), full-scale input 2.7 1.4 1.8 0.9 1.6 1.9 3.5 0.3 5.25 2.0 3.0 1.5 2.5 10 15 V VOL VOH IL COUT ISINK = 5MA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 6) 0.4 0.8 VDD - 0.5 0.01 10 15 V V A pF VSM VFLT SHDN = float SHDN = float VIH VIL VHYST IIN CIN VSH VSL SHDN = 0V or VDD 1.1 VDD / 2 100 VIN = 0V or VDD (Note 6) VDD - 0.4 0.4 4.0 VDD - 1.1 0.2 0.01 1 15 VDD 3.6V VDD > 3.6V 2.0 3.0 0.8 V V V A pF V V A V V nA V A k A F
18 SHDN = 0V 0.1
mA
A mV 3
Power-Supply Rejection (Note 7)
PSR
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+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, circuit of Figure 9, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low SCLK Low to CS Fall Setup Time DOUT Rise to SCLK Rise (Note 6) CS Pulse Width SYMBOL tACQ tDO tDV tTR fSCLK tCH tCL tCS0 tSTR tCS Figure 1, CLOAD = 50pF Figure 1, CLOAD = 50pF Figure 2, CLOAD = 50pF 0 200 200 50 0 240 CONDITIONS CS = VDD (Note 8) MAX124_ _C/E MAX124_ _M MIN 1.5 20 20 200 240 240 240 2.1 TYP MAX UNITS s ns ns ns MHz ns ns ns ns ns
Note 1: Tested at VDD = +2.7V. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 3: Offset nulled. Note 4: Sample tested to 0.1% AQL. Note 5: External load should not change during conversion for specified accuracy. Note 6: Guaranteed by design. Not subject to production testing. Note 7: Measured as [VFS (VDD(min)) - VFS (VDD(max))]. Note 8: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired.
+2.7V
6k DOUT 6k DGND a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL CLOAD = 50pF DOUT CLOAD = 50pF DGND
Figure 1. Load Circuits for DOUT Enable Time
+2.7V
6k DOUT 6k DGND a) VOH to High-Z b) VOLto High-Z CLOAD = 50pF DOUT CLOAD = 50pF DGND
Figure 2. Load Circuits for DOUT Disable Time
4 _______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8
__________________________________________Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CLOAD = 20pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1242/43-01
MAX1242/MAX1243
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1242/43-02
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1242 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 2.25
MAX1242/43-03
2.00 1.75 SUPPLY CURRENT (mA) 1.50 1.25 MAX1243 1.00 CLOAD = 20pF 0.75 0.50 2.25 RL = CODE = 1010101000 2.75 3.25 3.75 4.25 4.75 CLOAD = 50pF
4.0 SHUTDOWN SUPPLY CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.25 2.75 3.25 3.75 4.25 4.75 MAX1242/MAX1243
2.5015 INTERNAL REFERENCE VOLTAGE (V)
CLOAD = 20pF MAX1242
CLOAD = 50pF
5.25
5.25
2.75
3.25
3.75
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX1242/43-04
SHUTDOWN CURRENT vs. TEMPERATURE
MAX1242/43-05
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1242 INTERNAL REFERENCE VOLTAGE (V) 2.500 VDD = 5V 2.499 VDD = 2.7V 2.498 2.497 2.496 2.495 2.494 VDD = 3.6V
MAX1242/43-06
1.3 MAX1242
3.00 2.75 SHUTDOWN CURRENT (A) 2.50 2.25 2.00 1.75 1.50 1.25 1.00
2.501
1.2 SUPPLY CURRENT (mA)
1.1
1.0 MAX1243 0.9 RLOAD = CODE = 1010101000 -60 -20 20 60 100 140
0.8
-60
-20
20
60
100
140
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX1242/43-07
INTEGRAL NONLINEARITY vs. TEMPERATURE
MAX1242/43-08
INTEGRAL NONLINEARITY vs. CODE
MAX1242/43-09
0.30 0.25 0.20 INL (LSB)
0.30 VDD = 2.7V 0.25 0.20 INL (LSB) 0.15 0.10 MAX1242 0.05
0.15 0.10 0.05 INL (LSB) 0 -0.05 -0.10
0.15 0.10 0.05 0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 SUPPLY VOLTAGE (V) MAX1242
MAX1243 0 -60 -40 -20 0
MAX1243 -0.15 20 40 60 80 100 120 140 0 256 TEMPERATURE (C) 512 CODE 768 1024
_______________________________________________________________________________________
5
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
______________________________________________________________Pin Description
PIN 1 2 NAME VDD AIN Positive Supply Voltage: +2.7V to +5.25V Sampling Analog Input, 0V to VREF range Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1242/MAX1243 down to 15A (max) supply current. Both MAX1242 and MAX1243 are fully operational with either SHDN high or floating. For the MAX1242, pulling SHDN high enables the internal reference, and letting SHDN float disables the internal reference and allows for the use of an external reference. Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242; bypass with a 4.7F capacitor. External reference voltage input for MAX1243, or for MAX1242 with the internal reference disabled. Bypass REF with a minimum of 0.1F when using an external reference. Analog and Digital Ground Serial-Data Output. Data changes state at SCLK's falling edge. High impedance when CS is high. Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high impedance. Serial-Clock Input. SCLK clocks data out at rates up to 2.1MHz. FUNCTION
3
SHDN
4 5 6 7 8
REF GND DOUT CS SCLK
_______________Detailed Description
Converter Operation
The MAX1242/MAX1243 use an input track/hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 10-bit output. Figure 3 shows the MAX1242/MAX1243 in their simplest configuration. The MAX1242/MAX1243 convert input signals in the 0V to VREF range in 9s, including T/H acquisition time. The MAX1242's internal reference is trimmed to 2.5V, while the MAX1243 requires an external reference. Both devices accept external reference voltages from 1.0V to VDD. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (Ps). The MAX1242/MAX1243 have two modes: normal and shutdown. Pulling SHDN low shuts the device down and reduces supply current below 10A (VDD 3.6V), while pulling SHDN high or leaving it open puts the devices into operational mode. A conversion is initiated by pulling CS low. The conversion result is available at DOUT in unipolar serial format. The serial-data stream consists of a high bit, signaling the end of conversion (EOC), followed by the data bits (MSB first).
Track/Hold In track mode, the analog signal is acquired and stored in the internal hold capacitor. In hold mode, the T/H switch opens and maintains a constant input to the ADC's SAR section.
During acquisition, the analog input AIN charges capacitor CHOLD. Bringing CS low ends the acquisition interval. At this instant, the T/H switches the input side of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at the comparator's input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10bit resolution. This action is equivalent to transferring a charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. At the conversion's end, the input side of C HOLD switches back to AIN, and C HOLD charges to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and the minimum time needed for the signal to be acquired. Acquisition time is calculated by: tACQ = 7(RS + RIN) x 16pF
Analog Input
Figure 4 illustrates the sampling architecture of the analog-to-digital converter's (ADC's) comparator. The fullscale input voltage is set by the voltage at REF.
6
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+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
+2.7V to +5.25V CAPACITIVE DAC 4.7F 0.1F 1 ANALOG INPUT 0V TO VREF 2 VDD AIN SCLK CS 8 7 AIN SERIAL INTERFACE HOLD 6 5 TRACK INPUT CHOLD -+ 16pF CSWITCH TRACK 9k RIN HOLD AT THE SAMPLING INSTANT, THE INPUT SWITCHES FROM AIN TO GND. COMPARATOR ZERO REF
SHUTDOWN INPUT REFERENCE INPUT MAX1243 *4.7F, MAX1242 0.1F, MAX1243
3 4 C*
MAX1242 MAX1243 SHDN DOUT
REF GND
GND
Figure 3. Operational Diagram
Figure 4. Equivalent Input Circuit
where RIN = 9k, RS = the input signal's source impedance, and tACQ is never less than 1.5s. Source impedances below 4k do not significantly affect the ADC's AC performance. Higher source impedances can be used if a 0.01F capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's input signal bandwidth.
Input Bandwidth The ADC's input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. Analog Input Protection Internal protection diodes, which clamp the analog input to VDD and GND, allow the input to swing from GND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, limit the input current to 2mA.
Internal Reference (MAX1242) The MAX1242 has an on-chip voltage reference trimmed to 2.5V. The internal reference output is connected to REF and also drives the internal capacitive DAC. The output can be used as a reference voltage source for other components and can source up to 400A. Bypass REF with a 4.7F capacitor. Larger capacitors increase wake-up time when exiting shutdown (see Using SHDN to Reduce Supply Current). The internal reference is enabled by pulling the SHDN pin high. Letting SHDN float disables the internal reference, which allows the use of an external reference, as described in the External Reference section. External Reference The MAX1242/MAX1243 operate with an external reference at the REF pin. To use the MAX1242 with an external reference, disable the internal reference by letting SHDN float. Stay within the voltage range 1.0V to VDD to achieve specified accuracy. The minimum input impedance is 18k for DC currents. During conversion, the external reference must be able to deliver up to 250A of DC load current and have an output impedance of 10 or less. The recommended minimum value for the bypass capacitor is 0.1F. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
_______________________________________________________________________________________
7
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
Serial Interface
Initialization after Power-Up and Starting a Conversion
When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7F reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 10s after the power supplies have stabilized. No conversions should be performed during these times. To start a conversion, pull CS low. At CS's falling edge, the T/H enters its hold mode and a conversion is initiated. After an internally timed conversion period, the end of conversion is signaled by DOUT pulling high. Data can then be shifted out serially with the external clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by shutting down the MAX1242/MAX1243 between conversions. Figure 6 shows a plot of average supply current vs. conversion rate. Because the MAX1243 uses an external reference voltage (assumed to be present continuously), it "wakes up" from shutdown more quickly, providing lower average supply currents. The wakeup time, tWAKE, is the time from SHDN deasserted to the time when a conversion may be initiated (Figure 5). For the MAX1242, this time depends on the time in shutdown (Figure 7) because the external 4.7F reference bypass capacitor loses charge slowly during shutdown. The MAX1243's wake-up time is largely dependent on the external reference's power-up time. If the external reference is not shut down, the wake-up time is approximately 4s.
COMPLETE CONVERSION SEQUENCE CS tWAKE SHDN
DOUT CONVERSION 0 POWERED UP POWERED DOWN CONVERSION 1 POWERED UP
Figure 5. Shutdown Sequence
MAX1242/43-07
VDD = VREF RLOAD = , CLOAD = 50pF SUPPLY CURRENT (A) 1000 CODE = 0101010100
MAX1243-fig06
10,000
1.0
0.8 POWER-UP DELAY (ms) MAX1243 VDD = 3V 1k 10k 100k
0.6
100
MAX1242 VDD = 5V MAX1242 VDD = 3V
0.4
10
0.2
1 0.1 1 10 100 CONVERSIONS/SEC
0.0 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (sec)
Figure 6. Average Supply Current vs. Conversion Rate
8
Figure 7. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown
_______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
CS 1 SCLK DOUT EOC INTERFACE IDLE TRACK/HOLD TRACK STATE CONVERSION IN PROGRESS HOLD 7.5s (tCONV) CYCLE TIME 0s EOC CLOCK OUT SERIAL DATA TRACK 12.5 x 0.476s = 5.95s TOTAL = 13.7s 0s 0.24s (tCS) SUB BITS TRAILING ZEROS IDLE HOLD B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 4 8 12 16
Figure 8a. Interface Timing Sequence
CS 1 SCLK DOUT EOC INTERFACE IDLE TRACK/HOLD TRACK STATE CONVERSION IN PROGRESS HOLD 7.5s (tCONV) CYCLE TIME 0s EOC CLOCK OUT SERIAL DATA TRACK 10.5 x 0.476s = 5s TOTAL = 12.74s 0.24s (tCS) IDLE HOLD B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 4 8
Figure 8b. Interface Timing Sequence--Minimum Cycle Time
CS tCS0
tCS
... ...
tCH tDO
SCLK tDV DOUT tAP tSTR (HOLD) tCONV
tCL B0 S1 S0
tTR
... ...
INTERNAL T/H
(TRACK/ACQUIRE)
(TRACK/ACQUIRE)
Figure 9. Detailed Serial-Interface Timing
_______________________________________________________________________________________ 9
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
External Clock
The actual conversion does not require the external clock. This allows the conversion result to be read back at the P's convenience at any clock rate up to 2.1MHz. The clock duty cycle is unrestricted if each clock phase is at least 200ns. Do not run the clock while a conversion is in progress.
OUTPUT CODE 11...111 11...110 11...101 FULL-SCALE TRANSITION
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing diagrams of Figures 8 and 9 outline serial-interface operation. A CS falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK must be kept low during the conversion. An internal register stores the data when the conversion is in progress. EOC is signaled by DOUT going high. DOUT's rising edge can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on SCLK's falling edge. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits, two sub-bits, and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CS, produce trailing zeros at DOUT and have no effect on converter operation. For minimum cycle time, use DOUT's rising edge as the EOC signal and then clock out the data with 10.5 clock cycles at full speed (Figure 8b). Pull CS high after reading the conversion's LSB. After the specified minimum time, tCS, pull CS low again to initiate the next conversion.
FS = VREF - 1LSB V 1LSB = REF 1024 00...011 00...010 00...001 00...000 0 1 2 3 INPUT VOLTAGE (LSB) FS FS - 3/2LSB
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF - 1LSB, Zero Scale (ZS) = GND
I/O SCK MISO +3V
CS SCLK DOUT
SS a) SPI CS SCK MISO +3V CS
MAX1242 MAX1243
SCLK DOUT
Output Coding and Transfer Function
The data output from the MAX1242/MAX1243 is binary. Figure 10 depicts the nominal transfer function. Code transitions occur halfway between successive-integer LSB values. If VREF = 2.5V, then 1LSB = 2.44mV or 2.5V / 1024.
b) QSPI
SS
MAX1242 MAX1243
I/O SK SI
CS SCLK DOUT
__________Applications Information
Connection to Standard Interfaces
The MAX1242/MAX1243 serial interface is fully compatible with SPI, QSPI, and Microwire standard serial interfaces (Figure 11).
c) MICROWIRE
MAX1242 MAX1243
Figure 11. Common Serial-Interface Connections to the MAX1242/MAX1243
10 ______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
1ST BYTE READ SCLK CS tCONV DOUT D9 MSB EOC D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB S1 S0 HIGH-Z 2ND BYTE READ
Figure 12. SPI/Microwire Serial-Interface Timing (CPOL = CPHA = 0)
SCLK CS tCONV DOUT D9 MSB EOC D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB S1 S0 HIGH-Z
Figure 13. QSPI Serial-Interface Timing (CPOL = CPHA = 0)
If a serial interface is available, set the CPU's serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 2.1MHz. 1) Use a general-purpose I/O line on the CPU to pull CS low. Keep SCLK low. 2) Wait the maximum conversion time specified before activating SCLK. Alternatively, look for a DOUT rising edge to determine the end of conversion. 3) Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the DOUT conversion. DOUT output data transitions on SCLK's falling edge and is available in MSB-first format. Observe the SCLK-to-DOUT valid timing characteristic. Data can be clocked into the P on SCLK's rising edge. 4) Pull CS high at or after the 11th falling clock edge. If CS remains low, the two sub-bits and trailing zeros are clocked out after the LSB. 5) With CS = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CS low. If a conversion is aborted by pulling CS high before the conversion's end, wait the minimum acquisition time, tACQ, before starting a new conversion. Data can be output in two bytes or continuously, as shown in Figures 8a and 8b. The bytes contain the result of the conversion padded with one leading 1, two sub-bits, and trailing 0s if SCLK is still active with CS kept low.
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0. Conversion begins with a CS falling edge. DOUT goes low, indicating a conversion is in progress. Wait until DOUT goes high or until the maximum specified 7.5s conversion time elapses. Two consecutive 1-byte reads are required to get the full 10+2 bits from the ADC. DOUT output data transitions on SCLK's falling edge and is clocked into the P on SCLK's rising edge. The first byte contains a leading 1, and seven bits of conversion result. The second byte contains the remaining three bits, two sub-bits, and three trailing zeros. See Figure 11 for connections and Figure 12 for timing.
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two 1-byte reads to acquire the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1242/MAX1243 require 11 clock cycles from the P to clock out the 10 bits of data. Additional clock cycles clock out the two sub-bits followed by trailing zeros (Figure 13). The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz.
Layout and Grounding
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package.
11
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 MAX1242/MAX1243
Ordering Information (continued)
PART MAX1242AESA MAX1242BESA MAX1242AMJA MAX1242BMJA MAX1243ACPA MAX1243BCPA MAX1243ACSA MAX1243BCSA MAX1243AEPA MAX1243BEPA MAX1243AESA MAX1243BESA MAX1243AMJA MAX1243BMJA TEMP. RANGE -40C to +85C -40C to +85C PINPACKAGE 8 SO 8 SO INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1
___________________Chip Information
TRANSISTOR COUNT: 2559 SUBSTRATE CONNECTED TO GND
-55C to +125C 8 CERDIP* -55C to +125C 8 CERDIP* 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO
-55C to +125C 8 CERDIP* -55C to +125C 8 CERDIP*
*Contact factory for availability and processing to MIL-STD-883. Note: Order the MAX1242A in place of the MAX1242C. Order the MAX1242B in place of the MAX1242D.
________________________________________________________Package Information
PDIPN.EPS SOICN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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